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| lt m4646 1 4646f for more information www.linear.com/ltm4646 typical application features description dual 10a or single 20a module regulator applications the lt m ? 4646 is a complete dual 10a output switching mode dc/dc power supply. included in the package are the switching controller, power fets, inductors, and all supporting components. operating from an input voltage range of 4.5v to 20v, the ltm4646 supports two outputs each with an output voltage range of 0.6v to 5.5v, set by external resistors. its high efficiency design delivers up to 10a continuous current for each output. only a few input and output capacitors are needed. the device supports frequency synchronization, multiphase operation, high efficiency light load operation and output voltage tracking for supply rail sequencing and has an onboard temperature diode per channel for device tempera - ture monitoring. high switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. fault protection features include overvoltage and overcur - rent protection. the power module is offered in a small footprint 11.25mm 15mm 5.01mm bga package. the ltm4646 is available with snpb or rohs compliant terminal finish. all registered trademarks and trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611. n dual 10a or single 20a output n wide input voltage range: 4.5v to 20v n 2.375v min with cpwr bias n output voltage range: 0.6v to 5.5v n 1.5% maximum total dc output error n multiphase current sharing n differential remote sense amplifier, each channel n current mode control/fast transient response n up to 96% efficiency n adjustable switching frequency (250khz to 1.3mhz) n frequency synchronization n overcurrent foldback protection n output overvoltage protection n internal or external compensation n built-in temperature monitoring diode n snpb or rohs compliant finish n 11.25mm 15mm 5.01mm bga package n point-of-load power supplies n telecom and networking equipment n industrial equipment n medical equipment click to view associated techclip videos. efficiency, 12v to 0.9v, 1.2v at 10a each run1 run2 v out1 v outs1 v in1 v in2 cpwr drv cc intv cc v fb1 vrng v outs1 ? comp1a comp1b track/ss1 v out2 v outs2 v fb2 v outs2 ? comp2a comp2b track/ss2 mode_pllin ltm4646 4646 ta01a 100f 4 115k v out2 1.2v at 10a 60.4k 30.1k 0.1f pins not used in this circuit: pgood1, pgood2, extv cc , temp1 + , temp1 ? , temp2 + , temp2 ? phasmd, clkout, sw1, sw2 0.1f 4.7f sgnd freq gnd 121k 100 f 4 10 f 4 v in 4.5v to 20v v out1 0.9v at 10a 130k output current (a) 1 2 3 4 5 6 7 8 9 10 70 75 80 85 90 95 efficiency (%) 4646 ta01b 12v in to 1.2v eff, 500khz 12v in to 0.9v eff, 400khz
lt m4646 2 4646f for more information www.linear.com/ltm4646 cpwr, v i n1 , v i n2 ....................................... ? 0.3v to 22v v sw1 , v sw2 ................................................... ? 2v to 22v pgoo d1 , pgoo d2 , ru n1 , ru n2 , drv cc , intv cc , extv cc , v out1 , v out2 , v out s1 , v out s2 ..................................................... ? 0.3v to 6v track/s s1 , track/s s2 ............................. ? 0.3v to 5v freq, vrng, phasmd, mode_pllin ............................? 0.3v to intv cc +0.3 v out s1 ? (note 6) ....................................... ? 0.3v to v fb1 v out s2 ? (note 6) ..........................? 0.3v to intv cc + 0.3v com p1 a, com p2 a (note 6) ..................... ? 0.3v to 2.7v com p1 b, com p2 b, v fb1 , v fb2 ................. ? 0.3v to 2.7v drv cc peak output current ................................. 100ma internal operating temperature range (note 2) .................................. ? 40 c to 125 c storage temperature range .................. ? 55 c to 125 c peak solder reflow package body temperature .... 245 c pin configuration absolute maximum ratings (note 1) order information 1 a b c d e f g h j k l 2 3 4 5 top view bga package 88-lead (15mm 11.25mm 5..01mm) 6 7 8 v in1 sw1 run1 sw2 v out1 temp1 ? temp1 + temp2 ? temp2 + v outs1 ? v outs1 phasmd sgnd track/ss1 pgood1 drv cc v fb1 comp1b comp1a freq cpwr intv cc track/ss2 mode_ pllin clkout extv cc pgood2 v fb2 v outs2 comp2a comp2b vrng run2 sgnd v outs2 ? v out2 v in2 gnd gnd gnd gnd t jmax = 125c, jctop = 12.6c/w, jcbottom = 1.8c/w, jb = 2.3c/w, ja = 9.6c/w values defined per jesd51-12 weight = 2.1g part number ball finish part marking* package type msl rating temperature range (see note 2) device finish code ltm4646ey#pbf sac305 (rohs) ltm4646y e1 bga 3 ?40c to 125c ltm4646iy#pbf ltm4646y ltm4646iy snpb (63/37) ltm4646y e0 ? consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? recommended bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? bga package and tray drawings: www.linear.com/packaging http://www.linear.com/product/ltm4646#orderinfo lt m4646 3 4646f for more information www.linear.com/ltm4646 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range (note 2). specified as each individual output channel. t a = 25c, v in = 12v and v run1 , v run2 at 5v unless otherwise noted. per the typical application in figure 18. symbol parameter conditions min typ max units v in(dc) input dc voltage 2.375v with 5v external bias on cpwr, 4.5v min without bias l 2.375 20 v v cpwr(dc) input control power voltage input range of bias normally connected to v in 4.5 20 v v out1, 2 (range) output voltage range (note 8) l 0.6 5.5 v v out1(dc) , v out2(dc) output voltage, total variation with line and load c in = 10f 4, c out = 100f 4, ceramic v out = 1.5v l 1.4775 1.5 1.5225 v input specifications v run1 , v run2 run pin on/off threshold run rising 1.1 1.2 1.3 v v run1hys , v run2hys run pin on hysteresis 160 mv r run1 , r run2 run1, run2 resistance pull-down resistance 100 k i inrush(vin) input inrush current at start-up i out = 0a, c in = 10f 4, c ss = 0.01f, c out = 100f 4, v out1 = 1.5v, v out2 = 1.5v, v in = 12v 1 a i q(vin) input supply bias current i out = 0.1a, f sw = 1mhz, pulse-skipping mode i out = 0.1a, f sw = 1mhz, switching continuous shutdown, run = 0, v in = 12v 17 35 40 ma ma a i s(vin) input supply current v in = 4.5v, v out = 1.5v, i out = 10a, f sw = 1mhz v in = 12v, v out = 1.5v, i out = 10a, f sw = 1mhz 3.9 1.45 a a output specifications i out1(dc) , i out2(dc) output continuous current range v in = 12v, v out = 1.5v (notes 7, 8) 0 10 a ?v out1(line) /v out1 ?v out2(line) /v out2 line regulation accuracy v out = 1.5v, v in from 4.5v to 20v i out = 0a for each output l 0.01 0.025 %/v ?v out1(load) /v out1 ?v out2(load) /v out2 load regulation accuracy for each output, v out = 1.5v, 0a to 10a v in = 12v (note 7) l 0.15 0.3 % v out1(ac) , v out2(ac) output ripple voltage for each output, i out = 0a, c out = 100f 4, v out = 1.5v, frequency = 350khz 15 mv p-p f s (each channel) output ripple voltage frequency v in = 12v, v out = 1.5v, r freq = 115k (note 4) 350 khz ?v outstart (each channel) turn-on overshoot c out = 100f 4, v out = 1.5v, i out = 0a v in = 12v, c ss = 0.01f 10 mv t start (each channel) turn-on time c out = 100f 4, no load, track/ss with 0.01f to gnd, v in = 12v 5 ms ?v out(ls) (each channel) peak deviation for dynamic load load: 0a to 6a to 0a c out = 100f 4 v in = 12v, v out = 1.5v 50 mv t settle (each channel) settling time for dynamic load step load: 0a to 6a to 0a c out = 100f 4 v in = 12v, v out = 1.5v 20 s i out(pk) (each channel) output current limit v in = 12v, v out = 1.5v 20 a lt m4646 4 4646f for more information www.linear.com/ltm4646 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range (note 2). specified as each individual output channel. t a = 25c, v in = 12v and v run1 , v run2 at 5v unless otherwise noted. per the typical application in figure 18. symbol parameter conditions min typ max units control section v fb1 voltage at v fb1 pin i out = 0a, v out = 1.5v l 0.592 0.600 0.608 v v fb2 voltage at v fb2 pin i out = 0a, v out = 1.5v v fb2 is gained back up by 2x internal to 0.6v l 0.296 0.3 0.304 v i fb1 , i fb2 (note 6) 0 50 na v ovl1, v ovl2 feedback overvoltage lockout v fb1 rising v fb2 rising l l 0.630 0.315 0.645 0.323 0.660 0.330 v v i track/ss1 , i track/ss2 track pin soft-start pull-up current track/ss1,track/ss2 = 0v 1.0 a uvlo intv cc undervoltage lockout intv cc falling v in (note 6) intv cc rising v in (note 6) 3.3 3.7 4.2 4.5 v v t off(min) minimum top gate off-time (note 6) 90 ns t on(min) minimum top gate on-time (note 6) 30 ns r fbhi1 , r fbhi2 resistor between v outs1 , v outs2 and v fb1 , v fb2 pins for each output 60.05 60.4 60.75 k v pgood1 , v pgood2 low pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v ?2 0 2 a v pgood pgood trip level v fb with respect to set output voltage v fb ramping negative v fb ramping positive ?7.5 7.5 % % internal linear regulator drv cc internal drv cc voltage 6v < cpwr < 20v 5.0 5.3 5.6 v drv cc load regulation drv cc load regulation i cc = 0ma to 100ma ?1.3 ?3.0 % v extvcc extv cc switchover voltage extv cc ramping positive 4.4 4.6 4.8 v v extvcc(drop) extv cc dropout i cc = 20ma, v extvcc = 5v 80 120 mv v extvcc(hyst) extv cc hysteresis 200 mv frequency and clock synchronization frequency nominal nominal frequency r freq = 115k 300 350 400 khz frequency low lowest frequency r freq = 165k (note 5) 250 khz frequency high highest frequency r freq = 29.4k 1.17 1.3 1.43 mhz r mode_pllin mode_pllin input resistance mode_pllin to sgnd 600 k channel 2 phase v out2 phase relative to v out1 phasmd = sgnd phasmd = float phasmd = intv cc 180 180 240 deg deg deg clkout phase phase (relative to v out1 ) phasmd = sgnd phasmd = float phasmd = intv cc 60 90 120 deg deg deg v pllin high v pllin low clock input high level to mode_pllin clock input low level to mode_pllin 2 0.5 v v lt m4646 5 4646f for more information www.linear.com/ltm4646 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range (note 2). specified as each individual output channel. t a = 25c, v in = 12v and v run1 , v run2 at 5v unless otherwise noted. per the typical application in figure 18. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4646 is tested under pulsed load conditions such that t j t a . the ltm4646e is guaranteed to meet specifications from 0c to 125c internal temperature. specifications over the ?40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4646i is guaranteed over the full ?40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: two outputs are tested separately and the same testing condition is applied to each output. note 4: the switching frequency is programmable from 250khz to1.3mhz. note 5: ltm4646 device is optimized to operate from 300khz to 750khz. note 6: these parameters are tested at wafer sort. note 7: see output current derating curves for different v in , v out and t a . note 8: for 6v v in 20v, the 3.3 to 5v output current needs to be limited to 9a/channel. all other input and output combinations are 10a/ channel with recommended switching frequency included in the efficiency graphs. derating curves and airflow apply. symbol parameter conditions min typ max units f sync (each channel) frequency sync capture range mode_pllin clock duty cycle = 50% 250 1300 khz vrng i limit set current limit per channel vrng = intv cc , i out to 10a, i limit ~22a vrng = sgnd, i out to 5a, i limit ~11a 20 9 a a t d(pgood) delay from v fb fault (ov/uv) to pgood falling (note 6) 50 s t d(pgood) delay from v fb fault (ov/uv clear) to pgood (note 6) 20 s v temp1 , v temp2 temp diode voltage i temp = 100a 0.598 v tc v temp1,2 v temp temperature coefficient ?2.0 mv/ c lt m4646 6 4646f for more information www.linear.com/ltm4646 typical performance characteristics 0.9v single phase single output load transient response 1v single phase single output load transient response 1.2v single phase single output load transient response 1.5v single phase single output load transient response 1.8v single phase single output load transient response efficiency vs output current, v in = 5v efficiency vs output current, v in = 8v dual phase single output efficiency vs output current, v in = 12v efficiency vs output current, v in = 12v 5.0v out , 1.3mhz 3.3v out , 1.1mhz 2.5v out , 850khz 1.8v out , 700khz 1.5v out , 600khz 1.2v out , 500khz 1.0v out , 400khz 0.9v out , 400khz output current (a) 2 4 6 8 10 12 14 16 18 20 70 75 80 85 90 95 100 efficiency (%) 4646 g04 extv cc = 5v 50s/div i out 5a/div 0.9v out 33mv/div 4646 g05 c out = 470f poscap, 5m, 100f 4, ceramic c comp = 100pf, f = 350khz 50s/div i out 5a/div 1v out 33mv/div 4646 g06 c out = 470f poscap, 5m, 100f 4, ceramic c comp = 100pf, f = 350khz 50s/div i out 5a/div 1.2v out 33mv/div 4646 g07 c out = 470f poscap, 5m, 100f 4, ceramic c comp = 100pf, f = 350khz 50s/div i out 5a/div 1.8v out 33mv/div 4646 g09 c out = 100f 3, ceramic c comp = 100pf, c ff = 47pf f = 500khz 50s/div i out 5a/div 1.5v out 33mv/div 4646 g08 c out = 100f 3, ceramic c comp = 100pf, c ff = 47pf f = 450khz 50s/div i out 5a/div 1.5v out 33mv/div 4646 g08 c out = 100f 3, ceramic c comp = 100pf, c ff = 47pf f = 450khz output current (a) 1 2 3 4 5 6 7 8 9 10 70 75 80 85 90 95 100 efficiency (%) 4646 g01 3.3v out , 550khz 2.5v out , 550khz 1.8v out , 500khz 1.5v out , 450khz 1.2v out , 400khz 1.0v out , 350khz 0.9v out , 350khz 5.0v out , 900khz 3.3v out , 850khz 2.5v out , 750khz 1.8v out , 600khz 1.5v out , 550khz 1.2v out , 475khz 1.0v out , 400khz 0.9v out , 400khz output current (a) 1 2 3 4 5 6 7 8 9 10 70 75 80 85 90 95 100 efficiency (%) 4646 g02 5.0v out , 1.3mhz 3.3v out , 1.1mhz 2.5v out , 850khz 1.8v out , 700khz 1.5v out , 600khz 1.2v out , 500khz 1.0v out , 400khz 0.9v out , 400khz output current (a) 1 2 3 4 5 6 7 8 9 10 70 75 80 85 90 95 100 efficiency (%) 4646 g03 lt m4646 7 4646f for more information www.linear.com/ltm4646 typical performance characteristics two-phase switching and ripple short-circuit protection, no load short-circuit protection, 10a load single phase single output start-up, no load single phase single output start-up, 10a load 50s/div i out 5a/div 2.5v out 67mv/div 4646 g10 c out = 100f 2, ceramic c comp = 100pf, c ff = 47pf f = 500khz 50s/div i out 3.3a/div 3.3v out 67mv/div 4646 g11 c out = 100f 1, ceramic c comp = 100pf, c ff = 47pf f = 750khz 50s/div i out 3.3a/div 5v out 67mv/div 4646 g12 c out = 100f 1, ceramic c comp = 100pf, c ff = 47pf f = 950khz 50ms/div v out 0.5v/div i out 6.7a/div 4646 g13 12v in , 1.5v out at no load c out = 470f 1, 2.5v, sanyo poscap, 100f 4, 6.3v, ceramic soft-start capacitor = 0.1f use run pin to control start-up 20ms/div 4646 g14 v out 0.5v/div i out 6.7a/div 12v in , 1.5v out at 10a load c out = 470f 1, 2.5v, sanyo poscap, 100f 4, 6.3v, ceramic soft-start capacitor = 0.1f use run pin to control start-up 1s/div v out 5v/div v out 10mv/div 4646 g15 12v to 1v at 20a two-phase 12v to 1v at 350khz ripple at 20a load c out = 330 f, 9m, 100 f 4, ceramic 20ms/div v out 500mv/div i in 1a/div 4646 g16 v in = 12v v out = 1.5v i out = no load 20ms/div v out 500mv/div i in 1a/div 4646 g17 v in = 12v v out = 1.5v i out = 10a 2.5v single phase single output load transient response 3.3v single phase single output load transient response 5v single phase single output load transient response lt m4646 8 4646f for more information www.linear.com/ltm4646 pin functions v out1 ( h1, j1 - j2, k1 - k2, l1 - l2 ): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. there is a 49.9 resistor connected between v out1 and v outs1 to protect the output from an open v outs1 . review table5. see note 8 in the electrical characteristics section for output current guideline. gnd ( a3, a6-a7, b3, b6-b7, c3-c7, d6-d7, e6, e8, f5, f7, g6, g8, h6 - h7, j4 - j7, k3, k6 - k7, l3, l6 - l7 ) : power ground pins for both input and output returns. v out2 ( a1-a2, b1-b2, c1-c2, d1): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. there is a 49.9 resistor connected between v out2 and v outs2 to protect the output from an open v outs2 . review table5. see note 8 in the electrical characteristics section for output current guideline. v outs1 , v outs2 ( g2, e2 ): these pins are connected to the top of the internal top feedback resistor for each out - put. each pin can be directly connected to its specific output, or connected to the remote sense point of v out . it is important to connect these pins to their designated outputs for proper regulation. in paralleling modules, the v outs1 pin is left floating, and the v fb1 pin is connected to intv cc . this will disable chan - nel 1?s error amplifier and internally connect comp1a to comp2a. the pgood1 and track/ss1 will be disabled in this mode. channel 2 ? s error amplifier will regulate the two channel single output. see v fb pin description and applications information section. freq (f1): frequency set pin. a resistor from this pin to sgnd sets the operating frequency. the equation: 41550 f(khz) ? 2.2 = r freq (k) an external clock applied to mode_pllin should be within 30% of this programmed frequency to ensure frequency lock. see the applications information section. sgnd ( d3, h3): signal ground pin. return ground path for all analog and low power circuitry. tie a single con - nection to the output capacitor gnd in the application. see layout guidelines in figure 17. v fb1 ( g4 ): this pin is the + input to a unity gain differen - tial amplifier. this pin is connected to v outs1 with a 60.4k precision resistor internal. different output voltages can be programmed with an additional resistor between v fb1 and v outs1 ? pins. the differential amplifier is feeding back the divided down output voltage from a remote sense divider network to compare to the internal 0.6v reference. in 2-phase single output operation, tie the v fb1 pin to intv cc . see figure1 and applications information section for details. v fb2 ( e4): this pin is the + input to a non-inverting gain of two amplifier utilizing three resistors in the feedback network to develop a remote sense divider network. this pin is connected to v outs2 with an internal 60.4k preci- sion resistor. the v out2 voltage is divided down to 0.3v then gained back up to 0.6v to compare with the internal 0.6v reference. this technique provides for equivalent remote sensing on v out2 . see figure 1 and applications information section fordetails. track/ss1,track/ss2 ( h4, f2 ): output voltage tracking pin and soft-start inputs. each channel has a 1.0a pull- up current source. each pin can be programmed with a soft- start ramp rate up to the 0.6v internal reference level, then beyond this point the internal 0.6v reference will control the feedback loop. when one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set the soft-start ramp rate. the remaining channel can be set up as the slave, and have the master? s output applied through a voltage divider to the slave output? s track pin. this voltage divider is equal to the slave output? s feedback divider for coincidental tracking. see the applications information section. (recommended to use test points to monitor signal pin connections.) drv cc ( g7 ): internal 5.3v regulator output used to source the power mosfet drivers, and supply power to the intv cc input. a 4.7 f ceramic capacitor is needed on this pin to gnd. (recommended to use test points to monitor signal pin connections.) package row and column labeling may vary among module products. review each package layout carefully. lt m4646 9 4646f for more information www.linear.com/ltm4646 pin functions cpwr ( f8 ): input power to the control ic, and power to the drv cc regulator. this pin is connected to v in for normal 4.5v to 20v operation. for lower voltage inputs below 4.5v , cpwr can be powered with an external 5v bias. see application section. comp1a, comp2a ( g3, e3): current control threshold. these pins are the output of the error amplifier and the switching regulator? s compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v. comp1b, comp2b ( g1, e1 ): internal compensation network .these pins are to be connected to their respected compa pins. when utilizing specific external compensa - tion, then float these pins. mode_pllin ( f3 ): operation mode selection or external clock synchronization input. when this pin is tied to intv cc , forced continuous mode operation is selected. tying this pin to sgnd allows discontinuous mode operation. when an external clock is applied at this pin, both channels operate in forced continuous mode and synchronize to the external clock. this pin has an internal 600k pull-down resistor to sgnd. an external clock applied to mode_pllin should be within 30% of this programmed frequency to ensure frequency lock. clkout (f4 ): clock output with phase control using the phasmd pin to enable multiphase operation between devices. its output level swings between intv cc and sgnd. if clock input is present at the mode_pllin pin, it will be synchronized to the input clock, with phase set by the phasmd pin. if no clock is present at mode_pllin , its frequency will be set by the freq pin. to synchronize other controllers, it can be connected to their mode_pllin pins. see the applications information section. run1 , run2 ( h5, d5 ): run control pins. a voltage above 1.3v will turn on each channel in the module. a voltage below 1.0v on the run pin will turn off the related channel. each run pin has a 1.2a pull-up current, once the run pin reaches 1.2v an additional 4.5a pull-up current is added to this pin. a 100k resistor to ground is internal, and can be used with a pull-up resistor to v in to turn on the module using the external and internal resistor to program under voltage lockout. otherwise, an external enable signal or source can drive these pins directly below the 6v max. enabling either run pin will turn on the drv cc , and turn on the intv cc path for operation. see figure1 and applications section. phasmd ( h2 ): connect this pin to sgnd, intv cc , or floating this pin to select the phase of clkout and chan- nel 2. see electrical characteristics table and application section. pgood1, pgood2 ( g5, e5 ): output voltage power good indicator. open-drain logic output that is pulled to ground when the output voltage is not within 7.5% of the regula - tion point. see applications section. intv cc ( f6 ): supply input for internal circuitry (not including gate drivers). this bias is derived from drv cc internally. extv cc ( e7 ): external power input. when extv cc exceeds the switchover voltage (typically 4.6v), an internal switch connects this pin to drv cc and shuts down the internal regulator so that intv cc and gate drivers draw power from extv cc . the v in pin still needs to be powered up but draws minimum current. temp1 + ,temp1 ? and tem p2 + , tem p2 ? ( l8, k8 and b8, a8): onboard temperature diode for monitoring each channel with differential connections for noise immunity. v i n1 ( k4- k5, l4 - l5) and v i n2 ( a4- a5, b4 - b5 ): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capaci- tance directly between v in pins and gnd pins. v outs1 ? ( j3 ): differential output sense amplifier (? ) input of channel 1. connect this pin to the negative terminal of the output load capacitor of v out1 . v outs2 ? ( d4 ): differential output sense amplifier ( ?) input of channel 2. connect this pin to the negative ter - minal of the output load capacitor of v out2 . sw1 ( h8, j8) and sw2 ( c8, d8 ): switching node of each channel that is used for testing purposes. also an r-c snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. see the applications information section. vrng (d2): current limit adjustment range. tying this pin to intv cc sets full 10a current, or tying to sgnd will lower the current limit to 5a. default to intv cc . (recommended to use test points to monitor signal pin connections.) lt m4646 10 4646f for more information www.linear.com/ltm4646 block diagram figure 1. simplified ltm4646 block diagram + ? + ? + + ? ? + + + run1 and run2 separate: drv cc extv cc mode_pllin clkout phasmd run2 sgnd 100k power control logic block ss v in drv cc mtop2 c8 1f 0.47h gate drive internal comp comp2a track/ss1 freq vrng intv cc intv cc comp2b comp1a comp1b 115k 350khz sgnd run1 v in 4.7f 130k track/ss2 pgood2 sgnd c ss v fb1 0.555v pgood2 block ss sgnd 1a 0.645v 0.6v ref 50k r7 50k located near power stages 470pf v out2 60.4k 49.9 mbot2 1f 1a v fb2 v outs2 ? temp2 + temp2 ? v outs2 c out2 r fb3 30.1k gnd temp sensor sgnd v out2 v out2 1.2v/10a sw2 v in pgood1 gm ? + ? + ? + + v fb2 r fb2 60.4k c in3 10f 25v c in4 10f 25v sgnd c ss sgnd 100k intv cc 1f 1f gm ? + + sgnd 0.6v ref v fb1 v fb1 0.555v pgood1 block 0.645v ? + ? + located near power stages pnp 470pf temp1 + temp1 ? temp sensor v out1 60.4k 49.9 1 v fb1 v outs1 r fb1 40.2k v in mtop1 1f 0.47h gate drive mbot1 1f c out1 gnd v out1 1.5v/10a sw1 v in c in1 10f 25v c in2 10f 25v 100f 25v top g bot g drv cc ldo drv cc cpwr cpwr v outs1 ? v in 4.5v to 20v gnd run1 and run2 tied together: gnd internal comp x2 0.6v 0.3v see figure 18 2 pnp t soft-start = c ss 1a ? 0.6v )( r freq = 41550 f(khz) ? 2.2 )( r pullup = v in(min) ? 100k 1.3 ? 100k ) ( r pullup = v in(min) ? 50k 1.3 ? 50k ) ( 4646 f01 lt m4646 11 4646f for more information www.linear.com/ltm4646 decoupling requirements symbol parameter conditions min typ max units c in1, c in2 c in3, c in4 external input capacitor requirement (v in = 4.5v to 20v, v out1 = 1.5v) (v in = 4.5v to 20v, v out2 = 1.5v) i out1 = 10a 10f 2 (note 8) i out2 = 10a 10f 2 (note 8) 20 20 f f c out1 c out2 external output capacitor requirement (v in = 4.5v to 20v, v out1 = 1.5v) (v in = 4.5v to 20v, v out2 = 1.5v) i out1 = 10a (note 8) i out2 = 10a (note 8) 400 400 f f t a = 25c. use figure 1 configuration. operation power module description the ltm4646 is a dual-output standalone non-isolated switching mode dc/dc power supply. it can provide two 10a outputs with few external input and output capacitors and setup components. this module provides precisely regulated output voltages programmable via external resistors from 0.6v dc to 5.5v dc over 4.5v to 20v input voltages. the typical application schematic is shown in figure 18. see note 8 in the electrical characteristics sec - tion for output current guideline. the ltm4646 has dual integrated controlled-on time cur - rent mode regulators and built-in power mosfet devices with fast switching speed. the controlled on-time, valley current mode control architecture, allows for not only fast response to transients without clock delay, but also constant frequency switching at steady load condition. the typical switching frequency is 400khz. for switching- noise sensitive applications, it can be externally synchro - nized from 250khz to 1.3mhz. a resistor can be used to program a free run frequency on the freq pin. see the applications information section. with current mode control and internal feedback loop compensation, the ltm4646 module has sufficient sta- bility margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. optimized external compensation is supported by disconnecting the internal compensation. current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condi - tion. internal overvoltage and undervoltage comparators pull the open-drain pgood outputs low if the output feed - back voltage exits a 7.5% window around the regulation point. as the output voltage exceeds 7.5% above regula - tion, the bottom mosfet will turn on to clamp the output voltage. the top mosfet will be turned off. this overvolt - age protect is feedback voltage referred. pulling the run pins below 1.3v forces the regulators into a shutdown state, by turning off both mosfets. the track/ss pins are used for programming the out - put voltage ramp and voltage tracking during start-up or used for soft-starting the regulator. see the applications information section. the ltm4646 is internally compen - sated to be stable over all operating conditions. table 5 provides a guideline for input and output capacitances for several operating conditions. the ltpowercad ? will be provided for transient and stability analysis. the v fb1 pin is used to program the channel 1 output voltage with a single external resistor to ground, and v fb2 pin requires two resistors to program the output. both channel 1 and2 have remote sense capability. multiphase operation can be easily employed with the mode_pllin , phasmd, and clkout pins. up to 6 phases can be cascaded to run simultaneously with respect to each other by programming the phasmd pin to different levels. see the applications information section. high efficiency at light loads can be accomplished with selectable pulse-skipping operation using the mode_pllin . these light load features will accommodate battery operation. efficiency graphs are provided for light load operation in the typical performance characteristics section. each channel has temperature diode included inside the module to monitor the temperature of the module. see the applications information section for details. lt m4646 12 4646f for more information www.linear.com/ltm4646 the typical ltm4646 application circuit is shown in figure 18. external component selection is primarily determined by the maximum load current and output voltage. refer to table 5 for specific external capacitor requirements for particular applications. v in to v out step-down ratios there are restrictions in the maximum v in and v out step- down ratio that can be achieved for a given input voltage. each output of the ltm4646 is capable of a wide duty cycle that is limited by the minimum on-time t on(min) of 30ns defined as t on(min) < d/f sw for narrow duty cycle, where d is duty cycle (v out /v in ) and f sw is the switch - ing frequency. the minimum off-time of 90ns t off(min) < 1 ? d/f sw is required for higher duty cycles. see note8 in the electrical characteristics section for output current guideline. output voltage programming the pwm controller has an internal 0.6v reference voltage. as shown in figure 1, a 60.4k internal feedback resistor connects between the v outs1 to v fb1 and v outs2 to v fb2 . it is very important that these pins be connected to their respective outputs for proper feedback regulation. each channel has a 49.9 resistor connected from v outs1 and v outs2 to v out1 and v out2 , respectively. this is used to protect the output if v outsn is open or left unconnected. the v out1 output voltage will default to 0.6v with no feed - back resistor on v fb1 . adding a resistor r fb1 from v fb1 pin to v outs1 ? programs the output voltage: v out1 0.6v ? 60.4k r fb1 r fb1 the v out2 output voltage will default to 0.3v with no feed - back resistor on v fb2 . adding a resistor r fb2 from v fb2 pin to v outs2 ? , and the r fb3 resistor equal to ( 60.4k// r fb2 ) from v fb2 to sgnd programs the output voltage: v out2 0.6v ? 60.4k r fb2 r fb2 r fb3 60.4k || r fb2 60.4k ? r fb2 60.4k + r fb2 applications information the thevenin equivalent of the v out2 equation would be the 0.6v with a series resistance of (60.4k || r fb2 ), thus r fb3 connected to the series resistance would be (60.4k||r fb2 ) to equal the 0.3v reference. table 1. v fb1 , v fb2 , resistor table vs various output voltages v out1 0.6v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5.0v r fb1 open 90.9k 60.4k 40.2k 30.1k 19.1k 13.3k 8.25k v out2 0.3v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5.0v r fb2 open 90.9k 60.4k 40.2k 30.1k 19.1k 13.3k 8.25k r fb3 open 36.5k 30.1k 24.3k 20k 14.7k 11k 7.32k figure 2 shows the ltm4646 used in a 2- phase single output: tie the v fb1 pin to intv cc , which will disable channel 1? s error amplifier and internally connect comp2 to comp1 . tie any of the compensation components to the comp2 pin. the comp1 pin can be either left open or shorted to comp2 externally as shown. the, v outs1 , track/ss1 and pgood1 pins become non-operable and can be left open. to make a single-output converter of three or more phases, additional ltm4646 micromod - ules can be used. the first module should be tied the same way as the figure2. if only one more channel of an additional ltm4646 is needed, use channel 2 for the additional phase: ? tie the com p2 pin to the comp2 pin of the firstmodule. ? tie the ru n2 pin to the run pins of the first module. use 1/2 the value for r fb2 and r fb3 . ? tie v outs2 of the additional channel to v outs2 of the first module then to remote sense point. ? tie the v fb2 pin to the v fb2 pin of the first module. ? tie the v outs2 ? pin to the v outs2 ? pin of the firstmodule. ? tie the track/s s2 pin to the track/ss2 pin of the first module. if both channels are needed for four phases, the addi - tional ltm4646 module should be tied the same way as the first as shown in figure 2 to disable the second channel1?s ea: ? tie the v fb1 pin to the module?s own intv cc. lt m4646 13 4646f for more information www.linear.com/ltm4646 figure 2. 2-phase parallel configurations applications information ? tie the com p2 pin to the comp2 pin of the firstmodule. ? tie the run pins to the run pins of the first module. ? tie the v fb2 pin to the v fb2 pin of the first module. use 1/2 the value for r fb2 and r fb3 . ? tie the v outs2 ? pin to the v outs2 ? pin of the firstmodule. ? tie v outs2 of both modules together then to the remote sense output. ? tie the track/s s2 pin to the track/ss2 pin of the first module. see figure 20 for an example. input capacitors the ltm4646 module should be connected to a low ac impedance dc source. for the regulator input, four 10f input ceramic capacitors are used for rms ripple current. a 47f to 100f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. if low imped - ance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty-cycle can be estimated as: d v out v in without considering the inductor current ripple, for each output, the rms current of the input capacitor can be estimated as: i cin(rms) i out(max) % ? d ? 1 d ( ) in the above equation, % is the estimated efficiency of the power module. the bulk capacitor can be a switcher- rated aluminum electrolytic capacitor, polymer capacitor. the ltm4646 is designed for low output voltage ripple noise and good transient response. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output volt - age ripple and transient requirements. c out can be a low + + run1 pgood1 sw1 v out1 v outs1 freq v in1 v in2 cpwr drv cc intv cc intv cc extv cc phasmd v fb1 vrng v outs1 ? comp1a comp1b track/ss1 run2 pgood2 sw2 v out2 v outs2 v fb2 v outs2 ? comp2a comp comp2b track/ss2 mode_pllin temp1 + temp1 ? sgnd gnd temp2 + temp2 ? clkout ltm4646 4646 f02 pgood2 100f 3 run intv cc 10k v out 1.2v at 20a 60.4k 30.1k remote sensed gnd 150pf channel 2 temp monitor diode channel 1 temp monitor diode intv cc intv cc 100 f 3 115k 10 f 25v 4 4.5v to 20v 130k 100 f 25v comp 0.1 f 47pf 7.15k c comp 1500pf 470 f 2.5v poscap lt m4646 14 4646f for more information www.linear.com/ltm4646 applications information esr tantalum capacitor, low esr polymer capacitor or ceramic capacitor. the typical output capacitance range for each output is from 200f to 470f . additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 7.5a /s transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance. stability criteria are considered in the table 5 matrix, and ltpowercad will be provided for stability analysis. multiphase operation will reduce effective output ripple as a function of the num - ber of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. ltpowercad can calculate the output ripple reduction as the number of implemented phases increases by n times. continuous and discontinuous mode operation if the mode_pllin pin is tied to intv cc or an external clock is applied to mode_pllin , the ltm4646 will be forced to operate in continuous mode. with load current less than one-half of the full load peak-to-peak ripple, the inductor current valley can drop to zero or become nega - tive. this allows constant-frequency operation but at the cost of low efficiency at light loads. if the mode_pllin pin is left open or connected to sig - nal ground, the channel will transition into discontinu - ous mode operation, where a current reversal compara - tor shuts off the bottom mosfet as the inductor current approaches zero, thus preventing negative inductor cur - rent and improving light-load efficiency. in this mode, both switches can remain off for extended periods of time. as the output capacitor discharges by load current and the output voltage droops lower, ea will eventually move the ith voltage above the zero current level (0.8v) to initiate another switching cycle. multiphase operation for output loads that demand more than 10a of current, two outputs in ltm4646 or even multiple ltm4646s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripple. the mode_pllin pin allows the ltm4646 to synchronize to an external clock (between 250khz and 1.3mhz) and the internal phase-locked loop allows the ltm4646 to lock onto an incoming clock phase as well. the clkout signal can be connected to the mode_pllin pin of the following stage to line up both the frequency and the phase of the entire system. tying the phasmd pin to intv cc , sgnd, or floating the pin will select v out2 and clkout phases relative to v out1 . up to of 12 phases can be cascaded to run simultaneously with respect to each other by programming the phasmd pin of each ltm4646 channel to different levels. figure 3 shows a 2-phase design, 4-phase design and a 6-phase design example for clock phasing with the phasmd table. a multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input volt - age is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. the ltm4646 device is an inherently current mode controlled device, so parallel modules will have very good current sharing. this will balance the thermals on the design. figure 19 shows an example of parallel operation and pin connection. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can - cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple cur - rent reduction as a function of the number of interleaved phases. figure4 shows this graph. lt m4646 15 4646f for more information www.linear.com/ltm4646 figure 3. examples of 2-phase, 4-phase, and 6-phase operation with phasmd table applications information figure 4. input rms current ratios to dc load current as a function of duty cycle duty cycle (v out /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4646 f04 rms input ripple current dc load current 6-phase 4-phase 3-phase 2-phase 1-phase 4646 f03 v out2 180 degrees 0 degrees mode_pllin v out1 phasmd clkout 2-phase design 4-phase design 6-phase design 90 degrees float v out2 180 degrees 0 degrees float float mode_pllin v out1 phasmd clkout v out2 270 degrees 90 degrees float float mode_pllin v out1 phasmd clkout 60 degrees 120 degrees v out2 180 degrees 0 degrees mode_pllin v out1 phasmd clkout v out2 240 degrees 60 degrees mode_pllin v out1 phasmd clkout v out2 300 degrees 120 degrees mode_pllin v out1 phasmd clkout phasmd sgnd controller1 controller2 clkout float intv cc 0 0 0 180 180 240 60 90 120 lt m4646 16 4646f for more information www.linear.com/ltm4646 applications information frequency selection and phase-locked loop (mode_ pllin and f set pins) the ltm4646 device is operated over a range of frequen - cies to improve power conversion efficiency . it is recom - mended to operate the lower output voltages or lower duty cycle conversions at lower frequencies to improve efficiency by lowering power mosfet switching losses. higher output voltages or higher duty cycle conversions can be operated at higher frequencies to limit inductor ripple current. the efficiency graphs will show an operat - ing frequency chosen for that condition an internal oscil- lator (clock generator) provides phase interleaved internal clock signals for individual channels to lock up to. the switching frequency and phase of each switching channel is independently controlled by adjusting the top mosfet turn-on time (on-time) through the one-shot timer. this is achieved by sensing the phase relationship between a top mosfet turn-on signal and its internal reference clock through a phase detector, and the time interval of the one-shot timer is adjusted on a cycle-by-cycle basis, so that the rising edge of the top mosfet turn-on is always trying to synchronize to the internal reference clock signal for the respective channel. the frequency of the internal oscillator can be pro - grammed from 250khz to 1.3mhz by connecting a resis - tor, r t , from the freq pin to signal ground (sgnd). the freq pin is regulated to 1.2v internally. the value of this resistor can be chosen according to the formula: r t (k) = 41550 f(khz) ? 2.2 for applications with stringent frequency or interfer - ence requirements, an external clock source connected to the mode_pllin pin can be used to synchronize the internal clock signals through a clock phase-locked loop (clockpll). the ltm4646 operates in forced continuous mode of operation when it is synchronized to the exter - nal clock. the external clock frequency has to be within 30% of the internal oscillator frequency for successful synchronization. the clock input levels should be no less than 2v for ? high ? and no greater than 0.5v for ? low?. the mode_pllin pin has an internal 600k pull-down resistor. during dynamic transient conditions either in the line volt - age or load current (e.g., load step or release), the top switch will turn on more or less frequently in response to achieve faster transient response. this is the benefit of the ltm4646? s controlled on-time, valley current mode architecture. however, this process may understandably lose phase and even frequency lock momentarily. for relatively slow changes, phase and frequency lock can still be maintained. for large load current steps with fast slew rates, phase lock will be lost until the system returns back to a steady-state condition . it may take up to several hundred microseconds to fully resume the phase lock, but the frequency lock generally recovers quickly, long before phase lock does. minimum on-time and minimum off-time minimum on-time t on is the smallest time duration that the ltm4646 is capable of turning on the top mosfet on either channel. it is determined by internal timing delays, and the gate charge required to turn on the top mosfet. the ltm4646 has a minimum on time of ~30ns, and far lower than what would be a concern based on the maxi - mum operating frequency of 1.3mhz . the below equation can be checked against the v in , v out , and (freq) frequency of operation to insure the minimum on time t on(min) is above 30ns. v out v in ? freq t on(min) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the output ripple will increase. the on-time can be increased by lowering the switching frequency. the below equation can be checked against the v in , v out, and (freq) frequency of operation to insure the minimum off time t off(min) is above 90ns. v out(max) v in(max) d max d max 1 ? freq ? t off(min) lt m4646 17 4646f for more information www.linear.com/ltm4646 applications information output voltage soft starting and tracking output voltage tracking can be programmed externally using the track/ss pins. the output can be tracked up and down with another regulator. the master regulator ?s output is divided down with an external resistor divider that is the same as the slave regulator?s feedback divider for to implement coincident tracking. the ltm4646 uses an accurate 60.4k resistor internally for the top feedback resistor for each channel. figure 5 shows an example of coincident tracking. slave 1 60.4k r fb ? v track v track is the track ramp applied to the slave?s track pin. v track has a control range of 0v to 0.6v, or the internal reference voltage. when the master? s output is divided down with the same resistor values used to set the slave ?s output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slave? s regulation point. voltage tracking is disabled when v track/ss is more than 0.6v. r tb in figure 5 will be equal to the r fb for coincident track - ing. figure 6 shows the coincident tracking waveforms. the track/ss pins can be controlled by a capacitor placed on the regulator track/ss pin to ground. a 1.0a current source will charge the track/ss pin up to the voltage reference and then proceed up to intv cc . after the 0.6v ramp, the track/ss pin will no longer be in control, and the internal voltage reference will control output regu- lation from the feedback divider. foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. the track/ss pins are pulled low when the run pin is below 1.2v. the total soft-start time can be calculated as: t soft-start c ss 1.0a ? 0.6v ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the mas - ter? s track/ss pin. as mentioned above, the track/ss pin has a control range from 0 to 0.6v. the master?s track/ss pin slew rate is directly equal to the master?s output slew rate in volts per second. the equation: mr sr ? 60.4k r ta where mr is the master? s output slew rate and sr is the slave ? s output slew rate in volts per second. when coincident tracking is desired, then mr and sr are equal, thus r ta is equal to 60.4k. r tb is derived from equation: r tb 0.6v v fb 60.4k v fb r fb v track r ta where v fb is the feedback voltage reference of the regula - tor, and v track/ss is 0.6v. since r ta is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r tb is equal to r fb with v fb = v track/ss . in ratiometric tracking, a different slew rate may be desired for the slave regulator. r tb can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. for example, mr = 20v/s, and sr = 15v/s. then r ta = 80.6k. solve for r tb to equal to 80.6k. each of the track/ss pins will have the 1.0a current source on when a resistive divider is used to implement tracking on that specific channel. this will impose an off - set on the track/ss pin input. smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4k is used then a 6.04k can be used to reduce the track/ss pin offset to a negligible value. power good each pgood pin is connected to an internal open-drain n-channel mosfet. an external resistor or current source can be used to pull this pin up to 6v (e.g., v out1,2 or drv cc ). overvoltage or undervoltage comparators (ov, uv) turn on the mosfet and pull the pgood pin low when the feedback voltage is outside the 7.5% window of the reference voltage. the pgood pin is also pulled low when the channel?s run pin is below the 1.2v threshold lt m4646 18 4646f for more information www.linear.com/ltm4646 applications information figure 6. output coincident tracking waveform figure 5. example of output tracking application circuit time master output slave output output voltage 4646 f06 + + + run1 pgood1 sw1 v out1 v outs1 freq v in1 v in2 cpwr drv cc intv cc intv cc extv cc phasmd v fb1 vrng v outs1 ? comp1a comp1b track/ss1 run2 pgood2 sw2 v out2 v outs2 v fb2 v outs2 ? comp2a comp2b track/ss2 mode_pllin temp1 + temp1 ? sgnd gnd temp2 + temp2 ? clkout ltm4646 4646 f05 v out1 pgood2 100f 4 run1 intv cc 10k v out2 0.9v at 10a r fb 121k 40.2k remote sensed gnd 100pf r tb 121k r ta 60.4k channel 2 temp monitor diode channel 1 temp monitor diode intv cc intv cc 60.4k 100 f 4 100pf 0.1 f intv cc pgood1 v out1 1.2v at 10a 4.7 f 115k 10 f 25v 4 4.5v to 20v 130k 100 f 25v 10k ramp time t softstart = (c ss /1.0 a) ? 0.6v run1 470 f 2.5v poscap 470 f 2.5v poscap lt m4646 19 4646f for more information www.linear.com/ltm4646 applications information (hysteresis applies), or in undervoltage lockout (uvlo). in an overvoltage (ov) condition, mt is turned off and mb is turned on immediately without delay and held on until the overvoltage condition clears. this happens regardless of any other condition as long as the run pin is enabled. for example, upon enabling the run1 pin, if v out is prebi - ased at more than 7.5% above the programmed regulated voltage, the ov stays triggered and bg forced on until v out is pulled a ~ 2.5% hysteresis below the 7.5% ov threshold. stability compensation the module has already been internally compensated for all output voltages. table 5 is provided for most applica - tion requirements. ltpowercad will be provided for other control loop optimization. use ltpowercad when tying output in parallel for higher current. external compensa- tion may be necessary. run enable the run pins have an enable threshold of 1.3v maximum, typically 1.2v with 100mv of hysteresis. they control the turn on each of the channels and drv cc and intv cc . a 100k resistor to ground is internal, and can be used with a pull-up resistor to v in to turn on the module using the external and internal resistor to program under voltage lock out. otherwise an external enable signal or source can drive these pins directly below the 6v max. the run pins can also be used for output voltage sequencing. in parallel operation the run pins can be tie together and controlled from a single control. see the typical application circuits in figure 21. drv cc , intv cc , and extv cc the ltm4646 module has an internal 5.3v low dropout regulator (drv cc ) that is derived from the input voltage through the cpwr (control power) pin. this regulator is used to power the intv cc control circuitry and the power mosfet drivers. this regulator can source up to 100ma, and typically uses ~50ma for powering the device at the maximum frequency. this internal 5.3v supply is enabled by either run1 or run2. extv cc allows an external 5v supply to power the ltm4646 and reduce power dissipation from the internal low dropout 5v regulator. the power loss savings can be calculated by: (cpwr ? 5v) ? 50ma = p loss extv cc has a threshold of 4.6v for activation, and a maxi - mum rating of 6v. when using a 5v input, connect this 5v input to extv cc also to maintain a 5v gate drive level. extv cc must sequence on after cpwr, and extv cc must sequence off before cpwr. cpwr (control power) the ltm4646 module has a cpwr pin that is biased with a supply voltage minimum of 4.5v, and up to v in maxi- mum in normal operation. when operating at lower input voltages below the 4.5v minimum, this pin can biased with an alternate source to power the controller section while operating down to the 2.375v minimum. for example, if 3.3v is supplied to v in , and a 5v bias with a 50ma capability was used to source the cpwr pin, then 3.3v input power conversion can be implemented. even though the cpwr can operate from 4.5v to 20v, a lower bias will lower the power loss if the module. see figure21 for an example. output remote sense the ltm4646? s differential output sensing schemes are distinct from conventional schemes where the regulated output and its ground reference are directly sensed with a difference amplifier whose output is then divided down with an external resistor divider and fed into the error amplifier input. this conventional scheme is limited by the common mode input range of the difference amplifier and typically limits differential sensing to the lower range of output voltages. the ltm4646 allows for seamless differential output sensing by sensing the resistively divided feedback volt - age differentially. this allows for differential sensing in the full output range from 0.6v to 5.5v. channel 1? s difference amplifier (diffamp) has a bandwidth of around 8mhz, and channel 2 ? s feedback amplifier has a bandwidth of around 4mhz , both high enough so as to not affect main loop compensation and transient behavior. lt m4646 20 4646f for more information www.linear.com/ltm4646 applications information the ltm4646 differential output sensing can correct for up to 300mv of common-mode deviation in the output ?s power and ground lines on channel 1, and 200mv on channel 2. to avoid noise coupling into the feedback voltages, the resistor dividers should be placed close to the v outs1 and v outs1 ? , or v outs2 and v outs2 ? pins. remote output and ground traces should be routed together as a differential pair to the remote output. for best accuracy, these traces to the remote output and ground should be connected as close as possible to the desired regulation point. review the parallel schematics in figure 20. output current range pin (vrng) tying the vrng pin to sgnd will set the output current to 5a, and ~ 9a current limit. tying the vrng pin to intv cc will set the output current to 10a, and ~ 20a current limit. sw pins the sw pins are generally for testing purposes by moni - toring these pins. these pins can also be used to dampen out switch node ringing caused by lc parasitic in the switched current paths. usually a series r-c combination is used called a snubber circuit. the resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing. if the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. the inductance is usually easier to predict. it combines the power path board inductance in combination with the mosfet inter - connect bond wire inductance. first the sw pin can be monitored with a wide bandwidth scope with a high fre - quency scope probe. the ring frequency can be measured for its value. the impedance z can be calculated: z(l) = 2fl where f is the resonant frequency of the ring, and l is the total parasitic inductance in the switch path. if a resistor is selected that is equal to z, then the ringing should be dampened. the snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. calculated by: z(c) = 1/(2fc). these values are a good place to start with. modification to these components should be made to attenuate the ringing with the least amount of power loss. temperature monitoring (temp1 and temp2) a diode connected pnp transistor is used for tempera - ture monitoring. measuring the absolute temperature of a diode is possible due to the relationship between current, voltage and temperature described by the classic diode equation: i d i s ? e v d ? v t or v d ? v t ? ln i d i s where i d is the diode current, v d is the diode voltage, is the ideality factor (typically close to 1.0) and i s (satu- ration current) is a process dependent parameter. v t can be broken out to: v t k ? t q where t is the diode junction temperature in kelvin, q is the electron charge and k is boltzmann?s constant. v t is approximately 26mv at room temperature ( 298k ) and scales linearly with kelvin temperature. it is this linear temperature relationship that makes diodes suitable tem - perature sensors. the i s term in the equation above is the extrapolated current through a diode junction when the diode has zero volts across the terminals. the i s term varies from process to process, varies with temperature, and by definition must always be less than i d . combining all of the constants into one term: k d ? k q where k d = 8.62 ? 5, and knowing ln(i d /i s ) is always positive because i d is always greater than i s , leaves us with the equation that: lt m4646 21 4646f for more information www.linear.com/ltm4646 figure 7. diode voltage v d vs temperature t(c) for different bias currents v d t(kelvin) ? k d ? ln i d i s where v d appears to increase with temperature. it is com- mon knowledge that a silicon diode biased with a current source has an approximate ? 2mv / c temperature rela - tionship (figure 7), which is at odds with the equation applications information k? d = k d ? in(10) = 198v/k yields ?v d = k? d ? t(kelvin) solving for temperature: t(kelvin) ?v d k' d , t(kelvin) [ c] 273.15, [ c] t(kelvin) 273.15 means that if we take the difference in voltage across the diode measured at two currents with a ratio of 10, the result - ing voltage is 198v per kelvin of the junction with a zero intercept at 0 kelvin. the diode connected pnp transistor at the temp + , temp ? pins can be used to monitor the internal temperature of the ltm4646. a general temperature moni - tor can be implemented by connecting a resistor between temp + and v in to set the current to 100a , grounding the temp ? pin, and then monitoring the diode voltage drop with temperature. a more accurate temperature monitor can be achieved with a circuit injecting two currents that are at a 10: 1 ratio. see ltc2997 data sheet. thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param- eters defined by je sd51 -12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a module ? package mounted to a hardware test board. the motivation for providing these thermal coefficients is found in jesd51-12 (? guidelines for reporting and using electronic package thermal information?). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulator? s thermal performance in their application at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin configuration section are in-and-of themselves not relevant to provid - ing guidance of thermal performance ; instead, the derat - ing curves provided in the data sheet can be used in a 4646 f07 temperature (c) ?173 ?73 27 127 diode voltage (v) 0.4 0.6 0.8 1.0 ?v d i d = 100a i d = 10a term, increases with temperature, reducing the ln(i d /i s ) absolute value yielding an approximate ? 2mv / c com - posite diode voltage slope. to obtain a linear voltage proportional to temperature, we cancel the i s variable in the natural logarithm term to remove the i s dependency from the following equation. this is accomplished by measuring the diode voltage at two currents i 1 , and i 2 , where i 1 = 10 ? i 2 . subtracting we get: ?v d t(kelvin) ? k d ? in i 1 i s t(kelvin) ? k d ? in i 2 i s combining like terms, then simplifying the natural log terms yields: ?v d = t(kelvin) ? k d ? in(10) and redefining constant lt m4646 22 4646f for more information www.linear.com/ltm4646 manner that yields insight and guidance pertaining to one ? s application-usage, and can be adapted to corre - late thermal performance to one ?s own application. the pin configuration section gives four thermal coefficients explicitly defined in jesd51-12; these coefficients are quoted or paraphrased below: 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air ther - mal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as ? still air? although natural convection causes the air to move. this value is determined with the part mounted to a 95mm 76mm pcb with four layers. 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambi- ent environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions don?t generally match the user?s application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions don?t generally match the user?s application. 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package. a graphical representation of the aforementioned ther - mal resistances is given in figure 8; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd51-12 or provided in the pin configuration section replicates or conveys normal oper - ating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the device?s total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module package? as the standard defines applications information figure 8. graphical representation of jesd51-12 thermal coefficients 4646 f08 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance lt m4646 23 4646f for more information www.linear.com/ltm4646 for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the package ? granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the ltm4646, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to differ - ent junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicity? but also, not ignoring practical realities? an approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea soft - ware is used to accurately build the mechanical geometry of the ltm4646 and the specified pcb with all of the cor - rect material coefficients along with accurate power loss source definitions ; (2) this model simulates a software- defined jedec environment consistent with jesd51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the ltm4646 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields a set of derating curves provided in other sections of this data sheet. after these laboratory tests have been performed, then the jb and ba are summed together to correlate quite well with the ltm4646 model with no airflow or heat sinking in a define chamber. this jb + ba value should accurately equal the ja value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. the ltm4646 has been designed to effectively remove heat from both the top and bottom of the package. the applications information bottom substrate material has very low thermal resistance to the printed circuit board. an external heat sink can be applied to the top of the device for excellent heat sinking with airflow. safety considerations the ltm4646 modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top mosfet fault. if the internal top mosfet fails, then turning it off will not resolve the overvoltage, thus the internal bottom mosfet will turn on indefinitely trying to protect the load. under this fault condition, the input voltage will source very large cur - rents to ground through the failed internal top mosfet and enabled internal bottom mosfet. this can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. a fuse or circuit breaker can be used as a secondary fault protector in this situation. the device does support over current protection. temperature diodes are provided for monitoring inter - nal temperature, and can be used to detect the need for thermal shutdown that can be done by controlling the run pin. power derating the 5v, 8v and 12v power loss curves in figures 9 through 11 can be used in coordination with the load current derating curves in figures 12 to 16 for calculating an approximate ja thermal resistance for the ltm4646 with airflow conditions. the power loss curves are taken at room temperature, and are increased with a 1.35 to 1.4 multiplicative factor at 125c. these factors come from the fact that the power loss of the regulator increases about 45% from 25 c to 150 c , thus a 50% spread lt m4646 24 4646f for more information www.linear.com/ltm4646 over 125c delta equates to ~0.35%/c loss increase. a 125c maximum junction minus 25c room temperature equates to a 100c increase. this 100c increase multi - plied by 0.35%/c equals a 35% power loss increase at the 125c junction, thus the 1.35 multiplier. the derating curves are plotted with v out1 and v out2 in parallel single output operation starting at 20a of load with low ambient temperature. the output voltages are 1v, 2.5v and 5v. these are chosen to include the lower and higher output voltage ranges for correlating the ther - mal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without airflow. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at ~ 120 c maximum while lowering output current or power while increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operating temperature specifies how much tem - perature rise can be allowed. as an example in figure 13, the load current is derated to ~14.5a at ~95c with no air or heat sink and the power loss for the 12v to 1.0v at 14.5a output is a ~ 3.04w loss. the ~ 3.04w loss is calculated with the ~2.25w room temperature loss from the 12v to 1.0v power loss curve at 14.5a, and the 1.35 multiplying factor at 125c ambient. if the 95c ambient temperature is subtracted from the 125c junction tem - perature, then the difference of 30c divided by 3.04w equals a 9.9c/w ja thermal resistance. table 2 speci - fies a 10.1c /w value which is pretty close. the airflow graphs are more accurate due to the fact that the ambient temperature environment is controlled better with airflow. as an example in figure 13, the load current is derated to ~16.5a at ~95c with 200lfm of airflow and the power loss for the 12v to 1.0v at 16.5a output is a 3.7w loss. the 3.7w loss is calculated with the ~2.75w room tem - perature loss from the 12v to 1.0v power loss curve at 16.5a, and the 1.35 multiplying factor at 125c ambient. if the 95c ambient temperature is subtracted from the 125c junction temperature, then the difference of 30c divided by 3.7w equals a 8. 1c /w ja thermal resistance. table 2 specifies a 8. 1c/w value which is pretty close. tables 2 through 4 provide equivalent thermal resistances for 1v, 2.5v and 5v outputs with and without airflow. the derived thermal resistances in tables 2 through 4 for the various conditions can be multiplied by the calcu - lated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the power loss curves and adjusted with applications information lt m4646 25 4646f for more information www.linear.com/ltm4646 applications information table 2. 1.0v output derating curve v in (v) power loss curve airflow (lfm) heat sink bga ja (c/w) figures 12, 13 5, 12 figure 9, 11 0 none 10.1 figures 12, 13 5, 12 figure 9, 11 200 none 8.1 figures 12, 13 5, 12 figure 9, 11 400 none 7.4 table 3. 2.5v output derating curve v in (v) power loss curve airflow (lfm) heat sink bga ja (c/w) figures 14, 15 5, 12 figure 9, 11 0 none 10.1 figures 14, 15 5, 12 figure 9, 11 200 none 8.0 figures 14, 15 5, 12 figure 9, 11 400 none 7.4 heat sink manufacturer part number website cool innovations 3-0504035ut411 www.coolinnovations.com thermally conductive adhesive tape pre-attached, chomerics p/n t411 table 5. capacitor matrix (all parameters are typical and dependent on board layout) vendors value part number vendors value part number taiyo yuden 22f, 25v c3216x7s0j226m panasonic sp 470f, 2.5v eefgx0e471r murata 22f, 25v grm31cr61c226ke15l panasonic poscap 470f, 2.5v 2r5tpd470m5 murata 100f, 6.3v grm32er60j107m panasonic poscap 470f, 6.3v 6tpd470m avx 100f, 6.3v 18126d107 mat panasonic 100f, 20v 20sep100m v out (v) c in (ceramic) c in (bulk)** c out1 (ceramic) c out2 (ceramic/bulk) c ff (pf) c comp (pf) v in (v) droop (mv) p-p deviation (mv) recovery time (s) load step (a/s) freq (khz) 0.9 22f 4 100f 100f 4 470f 2 100 5,12 26 52 30 5 400 1 22f 4 100f 100f 4 470f 2 100 5,12 26 52 30 5 400 1.2 22f 4 100f 100f 4 470f 2 100 5,12 30 60 30 5 500 1.5 22f 4 100f 100f 3 none 47 100 5,12 44 88 25 5 600 1.8 22f 4 100f 100f 3 none 47 100 5,12 44 88 25 5 700 2.5 22f 4 100f 100f 2 none 47 100 5,12 53 107 25 5 850 3.3 22f 4 100f 100f 1 none 47 100 5,12 67 133 20 3.3 1100 5 22f 4 100f 100f 1 none 47 100 5,12 67 185 20 3.3 1300 **bulk capacitance is optional if v in has very low input impedance. table 4. 5v output (extv cc electrically connected to 5v out ) derating curve v in (v) power loss curve airflow (lfm) heat sink bga ja (c/w) figures 16 12 figure 11 0 none 8.5 figures 16 12 figure 11 200 none 7.0 figures 16 12 figure 11 400 none 6.3 lt m4646 26 4646f for more information www.linear.com/ltm4646 figure 9. 5v in power loss curve figure 10. 8v in power loss curve figure 12. 5v to 1v derating curve, no heat sink, f sw = 350khz, extv cc electrically connected to v in figure 13. 12v to 1v derating curve, no heat sink, f sw = 400khz figure 14. 5v to 2.5v derating curve, no heat sink, f sw = 550khz, extv cc electrically connected to v in figure 15. 12v to 2.5v derating curve, no heat sink, f sw = 850khz applications information figure 11. 12v in power loss curve figure 16. 12v to 5v derating curve, no heat sink, f sw = 1.3mhz, extv cc electrically connected to v out ambient temperature (c) 60 70 80 90 110 100 120 0 4 8 12 20 16 maximum load current (a) 4646 g12 0lfm 200lfm 400lfm ambient temperature (c) 60 70 80 90 110 100 120 0 4 8 12 20 16 maximum load current (a) 4646 g13 0lfm 200lfm 400lfm ambient temperature (c) 60 70 80 90 110 100 120 0 4 8 12 20 16 maximum load current (a) 4646 g14 0lfm 200lfm 400lfm ambient temperature (c) 60 70 80 90 110 100 120 0 4 8 12 20 16 maximum load current (a) 4646 g15 0lfm 200lfm 400lfm ambient temperature (c) 60 70 80 90 110 100 120 0 4 8 12 20 16 maximum load current (a) 4646 g16 0lfm 200lfm 400lfm output current (a) 0 2 4 6 8 10 12 14 18 16 20 0.0 0.5 1.5 1.0 2.0 2.5 3.0 3.5 4.0 power loss (w) 4646 g09 3.3v out , 550khz 2.5v out , 550khz 1.8v out , 500khz 1.5v out , 450khz 1.2v out , 400khz 1.0v out , 350khz 0.9v out , 350khz output current (a) 0 2 4 6 8 10 12 14 18 16 20 0.0 0.5 1.5 1.0 2.0 2.5 3.0 3.5 5.0 4.0 4.5 power loss (w) 4646 g10 5.0v out , 900khz, extv cc = 5v out 3.3v out , 850khz 2.5v out , 750khz 1.8v out , 600khz 1.5v out , 550khz 1.2v out , 475khz 1.0v out , 400khz 0.9v out , 400khz output current (a) 0 2 4 6 8 10 12 14 18 16 20 1 2 3 4 6 5 power loss (w) 4646 g11 5.0v out , 1.3mhz, extv cc = 5v out 3.3v out , 1.1mhz 2.5v out , 850khz 1.8v out , 700khz 1.5v out , 600khz 1.2v out , 500khz 1.0v out , 400khz 0.9v out , 400khz lt m4646 27 4646f for more information www.linear.com/ltm4646 the above ambient temperature multiplicative factors. the printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. use a separated sgnd ground copper area for compo - nents connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules, tie the v out, v fb , and comp pins together. use an internal layer to closely connect these pins together. the track/ss pin can be tied a common capacitor for regulator soft-start. ? bring out test points on the signal pins for monitoring. figures 17a and 17b give a good example of the recom - mended layout. layout checklist/example the high integration of ltm4646 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout consid - erations are still necessary. ? use large pcb copper areas for high current paths, including v in , gnd, v out1 and v out2 . it helps to mini - mize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capac - itors next to the v in , gnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce mod - ule thermal stress, use multiple vias for interconnec - tion between top layer and other power layers. ? do not put vias directly on the pads, unless they are capped or plated over. applications information figure 17. recommended pcb layout gnd gnd v out2 gnd gnd v out1 v in2 v in2 (a) top layer 15mm x 11.25mm x 5.01mm 4646 f17a gnd gnd v out2 gnd gnd v out1 v in2 v in2 (b) bottom layer 15mm x 11.25mm x 5.01mm 4646 f17b lt m4646 28 4646f for more information www.linear.com/ltm4646 typical applications figure 19. 12v input to 0.75v at 20a two phase figure 18. 4.5v to 20v input to 1.5v dual output, at 10a each + run1 pgood1 sw1 v out1 v outs1 freq v in1 v in2 cpwr drv cc intv cc intv cc extv cc phasmd v fb1 vrng v outs1 ? comp1a comp1b track/ss1 run2 pgood2 sw2 v out2 v outs2 v fb2 v outs2 ? comp2a comp2b track/ss2 mode_pllin temp1 + temp1 ? sgnd gnd temp2 + temp2 ? clkout ltm4646 4646 f18 pgood2 100f 3 run1 intv cc 10k v out2 1.5v at 10a r fb 40.2k 24.3k remote sensed gnd 100pf c comp channel 2 temp monitor diode channel 1 temp monitor diode intv cc intv cc 40.2k 100 f 3 100pf c comp 0.1 f intv cc pgood1 v out1 1.5v at 10a 4.7 f 115k 10 f 25v 4 4.5v to 20v 130k 100 f 25v 10k 0.1 f run1 + run1 pgood1 sw1 v out1 v outs1 freq v in1 v in2 cpwr drv cc intv cc intv cc extv cc phasmd v fb1 vrng v outs1 ? comp1a comp1b track/ss1 run2 pgood2 sw2 v out2 v outs2 v fb2 v outs2 ? comp2a comp2b track/ss2 mode_pllin temp1 + temp1 ? sgnd gnd temp2 + temp2 ? clkout ltm4646 4646 f19 pgood2 100f 3 run1 intv cc 10k 240k 48.1k remote sensed gnd channel 2 temp monitor diode channel 1 temp monitor diode intv cc intv cc 100 f 3 4.7 f 115k 10 f 25v 4 4.5v to 14v 130k 100 f 25v 0.1 f comp v out 0.75v at 20a run1 1500pf c comp 100pf 7.15k + 470 f 2.5v poscap 2 lt m4646 29 4646f for more information www.linear.com/ltm4646 typical applications figure 20. four phase design 1v at 40a + + run1 pgood1 sw1 v out1 v outs1 freq v in1 v in2 cpwr drv cc intv cc extv cc phasmd v fb1 vrng v outs1 ? comp1a comp1b track/ss1 run2 pgood2 sw2 v out2 v outs2 v fb2 v outs2 ? comp2a comp2b track/ss2 mode_pllin temp1 + temp1 ? sgnd gnd temp2 + temp2 ? clkout u1 ltm4646 100f 4 run 1v at 40a 45.3k 18.2k remote sensed gnd 100pf channel 2 temp monitor diode channel 1 temp monitor diode intv cc intv cc _u1 100 f 4 intv cc _u1 4.7 f 115k 10 f 25v 3 4.5v to 16v 64.9k 100 f 25v 0.1 f comp run1 run pgood1 sw1 v out1 v outs1 freq v in1 v in2 cpwr drv cc intv cc extv cc phasmd v fb1 vrng v outs1 ? comp1a comp1b track/ss1 run2 pgood2 sw2 v out2 v outs2 v fb2 v outs2 ? comp2a comp2b track/ss2 mode_pllin temp1 + temp1 ? sgnd gnd temp2 + temp2 ? clkout u2 ltm4646 4646 f20 100f 4 470 f 2.5v x2 poscap run 100pf channel 2 temp monitor diode channel 1 temp monitor diode clk intv cc _u2 100 f 4 intv cc _u2 4.7 f 115k 10 f 25v 3 4.5v to 16v comp pgood intv cc _u2 run pgood v outs2 ? v fb track v outs2 ? v fb track clk lt m4646 30 4646f for more information www.linear.com/ltm4646 figure 21. 3.3v to 1.8v, and 2.5v at 10a each with pgood power up sequencing typical applications figure 22. efficiency, 3.3v in + run1 pgood1 sw1 v out1 v outs1 freq v in1 v in2 cpwr drv cc intv cc intv cc extv cc phasmd v fb1 vrng v outs1 ? comp1a comp1b track/ss1 run2 pgood2 sw2 v out2 v outs2 v fb2 v outs2 ? comp2a comp2b track/ss2 mode_pllin temp1 + temp1 ? sgnd gnd temp2 + temp2 ? clkout ltm4646 4646 f21 pgood2 100f 3 10k v out2 1.8v at 10a 30.1k 20k remote sensed gnd 100pf channel 2 temp monitor diode channel 1 temp monitor diode intv cc intv cc 100 f 2 4.7 f 115k 22 f 6.3v 4 3.3v 10k 220 f 6.3v 0.1 f pgood1 19.1k 100pf 0.1 f 3.3v 5v bias at 50ma v out1 2.5v at 10a v in 3.3v 49.9k 47pf pgood1 47pf 3.3v load current (a) 1 2 3 4 5 6 7 8 9 10 70 75 80 85 90 95 100 efficiency (%) 4646 f22 3.3v to 2.5v, 350khz 3.3v to 1.8v, 350khz lt m4646 31 4646f for more information www.linear.com/ltm4646 figure 23. 12v to 3.3v up to 10a, 5v to 1.8v at 10a typical applications + + run1 pgood1 sw1 v out1 v outs1 freq v in1 v in2 cpwr drv cc intv cc intv cc extv cc phasmd v fb1 vrng v outs1 ? comp1a comp1b track/ss1 run2 pgood2 sw2 v out2 v outs2 v fb2 v outs2 ? comp2a comp2b track/ss2 mode_pllin temp1 + temp1 ? sgnd gnd temp2 + temp2 ? clkout ltm4646 4646 f23 pgood2 100f 3 10k v out2 1.8v at 10a 30.1k 20k remote sensed gnd 100pf channel 2 temp monitor diode channel 1 temp monitor diode intv cc intv cc 100 f 2 intv cc 4.7 f 115k 22 f 16v 2 12v r4 10k 56 f 16v 22 f 6.3v 2 56 f 16v 0.1 f 13.3k 100pf 0.1 f 5v bias at 50ma v out1 3.3v up to 10a intv cc 5v 130k v in2 v in1 47pf 47pf lt m4646 32 4646f for more information www.linear.com/ltm4646 ltm4646 component bga pinout package description package row and column labeling may vary among module products. review each package layout carefully. pin id function pin id function pin id function pin id function pin id function pin id function a1 v out2 b1 v out2 c1 v out2 d1 v out2 e1 comp2b f1 freq a2 v out2 b2 v out2 c2 v out2 d2 vrng e2 v outs2 f2 track/ss2 a3 gnd b3 gnd c3 gnd d3 sgnd e3 comp2a f3 mode_pllin a4 v in2 b4 v in2 c4 gnd d4 v outs2 ? e4 v fb2 f4 clkout a5 v in2 b5 v in2 c5 gnd d5 run2 e5 pgood2 f5 gnd a6 gnd b6 gnd c6 gnd d6 gnd e6 gnd f6 intv cc a7 gnd b7 gnd c7 gnd d7 gnd e7 extv cc f7 gnd a8 temp2 ? b8 temp2 + c8 sw2 d8 sw2 e8 gnd f8 cpwr pin id function pin id function pin id function pin id function pin id function g1 comp1b h1 v out1 j1 v out1 k1 v out1 l1 v out1 g2 v outs1 h2 phasmd j2 v out1 k2 v out1 l2 v out1 g3 comp1a h3 sgnd j3 v outs1 ? k3 gnd l3 gnd g4 v fb1 h4 track/ss1 j4 gnd k4 v in1 l4 v in1 g5 pgood1 h5 run1 j5 gnd k5 v in1 l5 v in1 g6 gnd h6 gnd j6 gnd k6 gnd l6 gnd g7 drv cc h7 gnd j7 gnd k7 gnd l7 gnd g8 gnd h8 sw1 j8 sw1 k8 temp1 ? l8 temp1 + lt m4646 33 4646f for more information www.linear.com/ltm4646 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. package description please refer to http://www.linear.com/product/ltm4646#packaging for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view 3 see notes suggested pcb layout top view bga 88 0517 rev a ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? detail a pin 1 0.000 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 3.810 2.540 1.270 1.270 2.540 3.810 5.080 0.000 detail a ?b (88 places) f g h l j k e a b c d 2 1 4 3 5678 d a detail b package side view m x yzddd m zeee 0.630 0.025 ? 88x e b e e b a2 f g bga package 88-lead (15mm 11.25mm 5.01mm) (reference ltc dwg # 05-08-1541 rev a) 6 see notes symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 15.00 11.25 1.27 12.70 8.89 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 total number of balls: 88 dimensions notes ball ht ball dimension pad dimension substrate thk mold cap ht z detail b substrate a1 ccc z z // bbb z h2 h1 b1 mold cap 5. primary datum -z- is seating plane 6 package row and column labeling may vary among module products. review each package layout carefully ! lt m4646 34 4646f for more information www.linear.com/ltm4646 linear technology corporation 2018 lt 0118 ? printed in usa www.linear.com/ltm4646 related parts part number description comments ltm4642 dual 4a or single 8a step-down module regulator 4.5v v in 20v, 0.6v v out 5.5v, 9mm 11.25mm 4.92mm bga ltm4628 dual 8a or single 16a step down module regulator 4.5v v in 26.5v, 0.6v v out 5.5v, 15mm 15mm 4.32mm lga 15mm x 15mm 4.92 bga ltm4620a dual 13a or single 26a step-down module regulator 4.5v v in 16v, 0.6v v out 5.3v, 15mm 15mm 4.41mm lga, 15mm 15mm 5.01mm bga ltm4630a dual 18a or single 36a step-down module regulator 4.5v v in 15v, 0.6v v out 5.3v, 16mm 16mm 4.41mm lga, 16mm 16mm 5.01mm bga ltm4644 quad 4a step-down module regulator 4.5v v in 14v, 0.6v v out 5.5v, 9mm 15mm 5.01mm bga ltm4637 single 20a step-down module regulator 4.5v v in 20v, 0.6v v out 5.5v, 15mm 15mm 4.32mm lga, 15mm 15mm x 4.92mm bga LTM4645 single 25a step-down module regulator 4.7v v in 15v, 0.6v v out 1.8v, 9mm 15mm 3.51mm bga ltm4647 single 30a step-down module regulator 4.7v v in 15v, 0.6v v out 1.8v, 9mm 15mm 5.01mm bga package photo design resources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power search parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technology?s family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. bga |
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